1. Field Of The Invention
This invention relates to integrated circuits used in computers and, more particularly, to methods for accomplishing the design and optimization of a balanced tree for clock distribution with minimal skew.
2. History of the Prior Art
Most integrated circuits utilized in computers employ a periodic signal referred to as a clock signal to control the timing and throughput of the entire system. This clock signal must reach different functional sub-blocks such as latches and registers which are physically distributed over the area of the integrated circuit. If two such sub-blocks which are controlled by the same clock are at different distances from the clock driver, they will receive the clock signal at different times. This arrival time differential is called clock skew. One major source of clock skew is the delay due to the resistance and the capacitance of the metal lines used to distribute the clock signal to all of the sub-blocks of the integrated circuit. This skew can be minimized by distributing the clock signal such that the metal interconnection lines that carry this signal to all of the sub-blocks are of equal length. The network produced by this technique is referred to as an "H-clock tree" or a "balanced clock tree."
Even if all of the metal lines that carry the clock signal to the various sub-blocks of the integrated circuit have the same lengths there can be a skew between clock signals arriving at different sub-blocks. As was mentioned before, the skew is caused by the RC delay of the metal lines. Even though these lines have the same lengths and widths and thus have the same resistance, this does not necessarily mean that they will have the same capacitance because capacitance depends on the environment in which each of the individual lines runs. Many other metal lines run on the top, bottom, and sides of the clock lines in a custom integrated circuit. These other metal lines have different capacitive effects on the metal clock lines to the sub-blocks causing the RC delay for the different clock lines to be different. To compensate for these differences, it has been the practice for designers to compute the total capacitance of each branch of the clock line and then to adjust the capacitance of each branch manually by adding capacitance to lower valued branches to bring each to a common capacitance value. This process is iterative, very time consuming, and error prone; consequently, the process is very expensive.